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60 lines
1.9 KiB
Diff
60 lines
1.9 KiB
Diff
From 7ef01a32bd4e31ef761bc4f2a177abde0ff7d094 Mon Sep 17 00:00:00 2001
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From: Joachim Wiberg <troglobit@gmail.com>
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Date: Mon, 6 Apr 2026 14:15:56 +0200
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Subject: [PATCH 45/50] arm64: dts: mediatek: mt7988a: add USXGMII PCS nodes
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Add device nodes for the two USXGMII subsystem blocks (usxgmiisys0 at
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0x10080000 and usxgmiisys1 at 0x10081000), each referencing its clock,
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reset, and xfi_tphy SerDes PHY.
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Wire gmac1 to usxgmiisys1 and gmac2 to usxgmiisys0 via the pcs-handle
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property, so the Ethernet driver can discover the PCS at probe time.
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---
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arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 20 ++++++++++++++++++++
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1 file changed, 20 insertions(+)
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diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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index 366203a72d6d..5ae43390f6c2 100644
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--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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@@ -708,6 +708,24 @@ xfi_pll: clock-controller@11f40000 {
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#clock-cells = <1>;
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};
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+ usxgmiisys0: pcs@10080000 {
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+ compatible = "mediatek,mt7988-usxgmiisys";
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+ reg = <0 0x10080000 0 0x1000>;
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+ resets = <&watchdog 12>;
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+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
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+ phys = <&xfi_tphy0>;
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+ #pcs-cells = <0>;
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+ };
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+
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+ usxgmiisys1: pcs@10081000 {
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+ compatible = "mediatek,mt7988-usxgmiisys";
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+ reg = <0 0x10081000 0 0x1000>;
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+ resets = <&watchdog 13>;
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+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
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+ phys = <&xfi_tphy1>;
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+ #pcs-cells = <0>;
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+ };
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+
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efuse@11f50000 {
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compatible = "mediatek,mt7988-efuse", "mediatek,efuse";
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reg = <0 0x11f50000 0 0x1000>;
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@@ -979,12 +997,14 @@ gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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status = "disabled";
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+ pcs-handle = <&usxgmiisys1>;
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};
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gmac2: mac@2 {
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compatible = "mediatek,eth-mac";
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reg = <2>;
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status = "disabled";
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+ pcs-handle = <&usxgmiisys0>;
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};
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mdio_bus: mdio-bus {
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