diff --git a/board/aarch64/dts/styx/styx-a.dts b/board/aarch64/dts/styx/styx-a.dts new file mode 100644 index 00000000..1388ab6a --- /dev/null +++ b/board/aarch64/dts/styx/styx-a.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Marvell International Ltd. + * Copyright (C) 2024 Addiva Elektronik AB + * + * Device tree for Styx board +.*/ + +#include "styx.dtsi" +/ { + model = "Styx (rev A)"; + compatible = "styx,styx-a", + "styx,styx", + "marvell,armada-ap807-quad", + "marvell,armada-ap807"; +}; + +&sw3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* Can't use XSWP macro as port 0 does not have + * any LEDs attached to it. LEDs for port 10 seem + * to be wired to the corresponding SFP cage. Maybe + * we can apply a static workaround by binding port + * 10's green LED to "Special LED 1", so we can at + * least see link/act. + */ + port@0 { + reg = <0>; + label = "e16"; + nvmem-cells = <&base_mac 16>; + nvmem-cell-names = "mac-address"; + phy-mode = "10gbase-r"; + managed = "in-band-status"; + sfp = <&sfp3>; + }; + XSWCPU(9, &cp0_eth0); + sw3p10: XSWLINK(a, &sw2p10 &sw1p0); + }; + +}; + +&sw2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + sw2p0: XSWLINK(0, &sw1p0); + XSWP(9, "e15", 15, &sfp2); + sw2p10: XSWLINK(a, &sw3p10); + }; +}; + +&sw1 { + ports { + sw1p0: XSWLINK(0, &sw2p0 &sw3p10); + XSWP(9, "e14", 14, &sfp1); + XSWP(a, "e13", 13, &sfp0); + }; +}; diff --git a/board/aarch64/dts/styx/styx-b.dts b/board/aarch64/dts/styx/styx-b.dts new file mode 100644 index 00000000..c225ed27 --- /dev/null +++ b/board/aarch64/dts/styx/styx-b.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Marvell International Ltd. + * Copyright (C) 2024 Addiva Elektronik AB + * + * Device tree for Styx board + */ + +#include "styx.dtsi" +/ { + model = "Styx"; + compatible = "styx,styx-b", + "marvell,armada-ap807-quad", + "marvell,armada-ap807"; +}; + +&sw3 { + ports { + XSWCPU(0, &cp0_eth0); + sw3p9: XSWLINK(9, &sw2p0 &sw1p0); + XSWP(a, "e16", 16, &sfp3); + }; +}; + +&sw2 { + ports { + sw2p0: XSWLINK(0, &sw3p9); + XSWP(9, "e15", 15, &sfp2); + sw2p10: XSWLINK(a, &sw1p0); + }; +}; + +&sw1 { + ports { + sw1p0: XSWLINK(0, &sw2p10 &sw3p9); + XSWP(9, "e14", 14, &sfp1); + XSWP(a, "e13", 13, &sfp0); + }; +}; diff --git a/board/aarch64/dts/styx/styx.dts b/board/aarch64/dts/styx/styx.dts deleted file mode 100644 index 49a20342..00000000 --- a/board/aarch64/dts/styx/styx.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021 Marvell International Ltd. - * Copyright (C) 2023 Addiva Elektronik AB - * - * Device tree for Styx board - */ - -#include "styx.dtsi" diff --git a/board/aarch64/dts/styx/styx.dtsi b/board/aarch64/dts/styx/styx.dtsi index 938c14fa..d847d044 100644 --- a/board/aarch64/dts/styx/styx.dtsi +++ b/board/aarch64/dts/styx/styx.dtsi @@ -287,10 +287,33 @@ nvmem-cell-names = "mac-address"; \ phy-mode = "10gbase-r"; \ managed = "in-band-status"; \ - sfp = <&_sfp>; \ + sfp = <_sfp>; \ SWP_LED("sfp"); \ } +#define XSWCPU(_n, _eth) \ + port@_n { \ + reg = <0x ## _n>; \ + label = "cpu"; \ + ethernet = <_eth>; \ + phy-mode = "10gbase-r"; \ + fixed-link { \ + speed = <10000>; \ + full-duplex; \ + }; \ + } + +#define XSWLINK(_n, _link) \ + port@_n { \ + reg = <0x ## _n>; \ + link = <_link>; \ + phy-mode = "10gbase-r"; \ + fixed-link { \ + speed = <10000>; \ + full-duplex; \ + }; \ + } + #define GSWP(_n, _label, _mac_offs, _phy) \ port@_n { \ reg = <0x ## _n>; \ @@ -332,44 +355,6 @@ #address-cells = <1>; #size-cells = <0>; - port@9 { - reg = <0x9>; - label = "cpu"; - ethernet = <&cp0_eth0>; - phy-mode = "10gbase-r"; - fixed-link { - speed = <10000>; - full-duplex; - }; - }; - - sw3p10: port@a { - reg = <0xa>; - link = <&sw2p10 &sw1p0>; - phy-mode = "10gbase-r"; - fixed-link { - speed = <10000>; - full-duplex; - }; - }; - - /* Can't use XSWP macro as port 0 does not have - * any LEDs attached to it. LEDs for port 10 seem - * to be wired to the corresponding SFP cage. Maybe - * we can apply a static workaround by binding port - * 10's green LED to "Special LED 1", so we can at - * least see link/act. - */ - port@0 { - reg = <0>; - label = "e16"; - nvmem-cells = <&base_mac 16>; - nvmem-cell-names = "mac-address"; - phy-mode = "10gbase-r"; - managed = "in-band-status"; - sfp = <&sfp3>; - }; - GSWP(1, "e22", 22, sw3phy1); GSWP(2, "e21", 21, sw3phy2); GSWP(3, "e24", 24, sw3phy3); @@ -412,27 +397,6 @@ #address-cells = <1>; #size-cells = <0>; - sw2p0: port@0 { - reg = <0x0>; - link = <&sw1p0>; - phy-mode = "10gbase-r"; - fixed-link { - speed = <10000>; - full-duplex; - }; - }; - - sw2p10: port@a { - reg = <0xa>; - link = <&sw3p10>; - phy-mode = "10gbase-r"; - fixed-link { - speed = <10000>; - full-duplex; - }; - }; - - GSWP(1, "e10", 10, sw2phy1); GSWP(2, "e9", 9, sw2phy2); GSWP(3, "e12", 12, sw2phy3); @@ -441,7 +405,6 @@ GSWP(6, "e17", 17, sw2phy6); GSWP(7, "e20", 20, sw2phy7); GSWP(8, "e19", 19, sw2phy8); - XSWP(9, "e15", 15, sfp2); }; mdio { @@ -476,16 +439,6 @@ #address-cells = <1>; #size-cells = <0>; - sw1p0: port@0 { - reg = <0x0>; - link = <&sw2p0 &sw3p10>; - phy-mode = "10gbase-r"; - fixed-link { - speed = <10000>; - full-duplex; - }; - }; - GSWP(1, "e2", 2, sw1phy1); GSWP(2, "e1", 1, sw1phy2); GSWP(3, "e4", 4, sw1phy3); @@ -494,8 +447,6 @@ GSWP(6, "e5", 5, sw1phy6); GSWP(7, "e8", 8, sw1phy7); GSWP(8, "e7", 7, sw1phy8); - XSWP(9, "e14", 14, sfp1); - XSWP(a, "e13", 13, sfp0); }; mdio { diff --git a/board/aarch64/rootfs/boot/styx/styx.dtb b/board/aarch64/rootfs/boot/styx/styx.dtb new file mode 120000 index 00000000..000ce695 --- /dev/null +++ b/board/aarch64/rootfs/boot/styx/styx.dtb @@ -0,0 +1 @@ +styx-a.dtb \ No newline at end of file diff --git a/configs/aarch64_defconfig b/configs/aarch64_defconfig index 970e3fca..04ccdde5 100644 --- a/configs/aarch64_defconfig +++ b/configs/aarch64_defconfig @@ -31,7 +31,7 @@ BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.51" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="${BR2_EXTERNAL_INFIX_PATH}/board/aarch64/linux_defconfig" BR2_LINUX_KERNEL_DTS_SUPPORT=y -BR2_LINUX_KERNEL_INTREE_DTS_NAME="alder/alder styx/styx marvell/armada-3720-espressobin marvell/armada-3720-espressobin-emmc marvell/armada-3720-espressobin-v7 marvell/armada-3720-espressobin-v7-emmc marvell/armada-3720-espressobin-ultra marvell/cn9130-crb-A marvell/cn9130-crb-B microchip/sparx5_pcb135_emmc_no_psci" +BR2_LINUX_KERNEL_INTREE_DTS_NAME="alder/alder styx/styx-a styx/styx-b marvell/armada-3720-espressobin marvell/armada-3720-espressobin-emmc marvell/armada-3720-espressobin-v7 marvell/armada-3720-espressobin-v7-emmc marvell/armada-3720-espressobin-ultra marvell/cn9130-crb-A marvell/cn9130-crb-B microchip/sparx5_pcb135_emmc_no_psci" BR2_LINUX_KERNEL_CUSTOM_DTS_OVERLAY="${BR2_EXTERNAL_INFIX_PATH}/board/aarch64/dts" BR2_LINUX_KERNEL_DTB_KEEP_DIRNAME=y BR2_LINUX_KERNEL_INSTALL_TARGET=y diff --git a/configs/aarch64_minimal_defconfig b/configs/aarch64_minimal_defconfig index 171e4dae..3ca49d5c 100644 --- a/configs/aarch64_minimal_defconfig +++ b/configs/aarch64_minimal_defconfig @@ -31,7 +31,7 @@ BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.51" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="${BR2_EXTERNAL_INFIX_PATH}/board/aarch64/linux_defconfig" BR2_LINUX_KERNEL_DTS_SUPPORT=y -BR2_LINUX_KERNEL_INTREE_DTS_NAME="alder/alder styx/styx marvell/armada-3720-espressobin marvell/armada-3720-espressobin-emmc marvell/armada-3720-espressobin-v7 marvell/armada-3720-espressobin-v7-emmc marvell/armada-3720-espressobin-ultra marvell/cn9130-crb-A marvell/cn9130-crb-B microchip/sparx5_pcb135_emmc_no_psci" +BR2_LINUX_KERNEL_INTREE_DTS_NAME="alder/alder styx/styx-a styx/styx-b marvell/armada-3720-espressobin marvell/armada-3720-espressobin-emmc marvell/armada-3720-espressobin-v7 marvell/armada-3720-espressobin-v7-emmc marvell/armada-3720-espressobin-ultra marvell/cn9130-crb-A marvell/cn9130-crb-B microchip/sparx5_pcb135_emmc_no_psci" BR2_LINUX_KERNEL_CUSTOM_DTS_OVERLAY="${BR2_EXTERNAL_INFIX_PATH}/board/aarch64/dts" BR2_LINUX_KERNEL_DTB_KEEP_DIRNAME=y BR2_LINUX_KERNEL_INSTALL_TARGET=y