From 5cb17d69d4765928be5fcdf8cae35c1b4020e666 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mattias=20Walstr=C3=B6m?= Date: Wed, 29 Apr 2026 15:43:24 +0200 Subject: [PATCH] bpi-r3: Enable the PCI clock in device tree --- .../dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/board/aarch64/bananapi-bpi-r3/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi b/board/aarch64/bananapi-bpi-r3/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi index d220c512..abe2870c 100644 --- a/board/aarch64/bananapi-bpi-r3/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi +++ b/board/aarch64/bananapi-bpi-r3/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi @@ -24,6 +24,18 @@ https://github.com/openwrt/openwrt/blob/main/target/linux/mediatek/patches-6.12/ &secmon_reserved { reg = <0 0x43000000 0 0x40000>; }; +/* + * The T-PHY's pcie-phy sub-node only claims clk40m ("ref") in the SoC + * dtsi. CLK_TOP_PCIE_PHY_SEL ("da_ref") is left unclaimed, so the + * kernel's clk_disable_unused late_initcall gates it — killing the + * PCIe REFCLK output to the endpoint mid-probe. Wire it here so the + * clock stays enabled while the PHY is active. + */ +&pcie_port { + clocks = <&clk40m>, <&topckgen CLK_TOP_PCIE_PHY_SEL>; + clock-names = "ref", "da_ref"; +}; + &cpu_thermal { /delete-node/ trips; /delete-node/ cooling-maps;